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1 for more information www.linear.com/ltc7820 typical application features description fixed ratio high power inductorless (charge pump) dc/dc controller the lt c ? 7820 is a fixed ratio high voltage high power switched capacitor/charge pump controller. the device includes four n-channel mosfet gate drivers to drive external power mosfets in voltage divider, doubler or inverter configurations. the device achieves a 2:1 step- down ratio from an input voltage as high as 72v, a 1:2 step-up ratio from an input voltage as high as 36v, or a 1:1 inverting ratio from an input voltage up to 36v. each power mosfet is switched with 50% duty cycle at a constant pre-programmed switching frequency. system efficiency can be optimized to over 99%. the ltc7820 provides a small and cost effective solution for high power, non-isolated intermediate bus applications with fault protection. the ltc7820 switching frequency can be linearly programmed from 100khz to 1mhz . the device is available in a thermally enhanced 28-lead qfn package with some no-connect pins for high voltage compatible pin spacing. efficiency and power loss vs load current applications n low profile, high power density, capable of 500w+ n soft switching: 99% peak efficiency and low emi n v in max for voltage divider (2:1): 72v n v in max for voltage doubler (1 : 2)/inverter (1: 1) : 36v n wide bias v cc range: 6v to 72v n soft startup into steady state operation n 6.5v to 40v extv cc input for improved efficiency n input current sensing and overcurrent protection n wide operating frequency range: 100khz to 1mhz n output short-circuit/ov/uv protections with programmable timer and retry n thermally enhanced 28-pin 4mm 5mm qfn package n bus converters n high power distributed power systems n communications systems n industrial applications all registered trademarks and trademarks are the property of their respective owners. protected by u.s. patents, including 9484799. very high efficiency 5a voltage divider lt c7820 7820fc 7820 ta01a 1f 1f 0.1f 0.1f 0.1f 10 100 0.1f 12v 0.1f 10f 6 10k v cc v high_sense uv hys_prgm pgood freq fault gnd 10k intv cc g3 g4 intv cc timer g2 ltc7820 boost3 sw3 v low_sense 10k v low boost2 boost1 sw1 g1 intv cc extv cc run i sense + i sense ? 10k v in 48v/24v v out 24v/12v 5a* * load current applied after startup r sense 0.005 efficiency power loss f s = 100khz load current (a) 0 1 40k 2 3 4 5 95 96 97 98 99 100 4.7f 0 0.4 0.8 1.2 1.6 2.0 v in = 48v v out = 24v v in = 24v v out = 12v efficiency (%) power loss (w) 10 7820 ta01b 10f
2 for more information www.linear.com/ltc7820 pin configuration absolute maximum ratings v cc , v high_sense ....................................... C 0.3 v to 80v boost1 ..................................................... C 0. 3v to 86v boost2, boost3 ....................................... C 0. 3v to 51v sw1 .............................................................. C 5v to 80v sw3 .............................................................. C 5v to 45v v low , v low_sense ..................................... C 0.3 v to 45v i sense + , i sense C .......................................... C 0.3 v to 80v (boost1 - sw1), (boost2 - v low ) ............ C 0.3v to 6v (boost3 - sw3) .......................................... C 0. 3v to 6v intv cc , run ................................................ C 0. 3v to 6v extv cc , pgood ........................................ C 0.3 v to 45v hys_prgm , freq, timer, uv ............ C 0. 3v to intv cc fa u lt ......................................................... C 0. 3v to 80v intv cc peak current (note 10) ............................ 150 ma operating junction temperature range (notes 2, 11) ............................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (notes 1, 3) 9 10 top view ufd package 28-lead (4mm fault nc extv cc intv cc nc v cc 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, ja = 43c/w , jc(bottom) = 3.4c/w exposed pad (pin 29) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc7820eufd#pbf ltc7820eufd#trpbf 7820 28-lead (4mm 5mm) plastic qfn C40c to 125c ltc7820iufd#pbf ltc7820iufd#trpbf 7820 28-lead (4mm 5mm) plastic qfn C40c to 125c consult adi marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. http://www.linear.com/product/ltc7820#orderinfo lt c7820 7820fc
3 for more information www.linear.com/ltc7820 electrical characteristics symbol parameter conditions min typ max units input/output voltage v cc ic bias voltage range 6 72 v v vhigh_sense v high_sense voltage range (note 6) 0 72 v v vlow_sense v low_sense voltage range 0 36 v v vlow v low voltage range (note 5) 0 36 v i q input dc supply current shutdown normal operation v run = 0v v run = 5v, no switching 60 1.5 a ma v uvlo undervoltage lockout threshold v intvcc falling v intvcc rising 4.85 5.05 v v overcurrent protection i isense + i sense + pin current i sense + = i sense C = 24v 220 350 a pre-balance phase, v high_sense = 24v, i sense + = i sense C = 24v, v vlow = 12v, v vlow_sense = 11v 93 ma i isense C i sense C pin current l C5 1 5 a v isense current limit threshold (v isnese + C v isense C ) l 45 50 55 mv gate drivers r g2,4 pull-up on-resistance pull-down on-resistance 2.5 1.5 r g1,3 pull-up on-resistance pull-down on-resistance 2.4 1.1 g1 /g2 t d g1 off to g2 on delay time g2 off to g1 on delay time (note 4) 50 50 ns ns g3 /g4 t d g3 off to g4 on delay time g4 off to g3 on delay time (note 4) 60 60 ns ns g1 /g3 t d g1 on to g3 on delay time g3 off to g1 off delay time (note 4) 5 10 ns ns g2 /g4 t d g2 on to g4 on delay time g4 off to g2 off delay time (note 4) 5 10 ns ns run pin v run run pin on threshold v run rising l 1.1 1.22 1.35 v v run,hys run pin on hysteresis 80 mv intv cc regulator v intvcc_vcc intv cc voltage no load 6v < v cc < 72v, v extvcc = 0v 5.4 5.6 5.9 v intv cc load regulation i cc = 0 to 60ma, v extvcc = 0v 0.8 2 % v intvcc_ext intv cc voltage no load with extv cc 12v < v extvcc < 45v (note 7) 5.4 5.6 5.9 v intv cc load regulation with extv cc i cc = 0 to 50ma, v extvcc = 12v 0.5 2 % extv cc switchover voltage v extvcc ramping positive (note 9) 6.35 6.5 6.65 v extv cc hysteresis 400 mv v high_sense and v low_sense r vhigh_sense v high_sense to gnd resistance 1 m i vlow_sense v low_sense pin current v cc = 51v, v low_sense = 45v 1 10 a the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cc = 12v, v run = 5v, unless otherwise specified. lt c7820 7820fc
4 for more information www.linear.com/ltc7820 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc7820 is tested under pulsed load conditions such that t j t a . the ltc7820e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc7820i is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 43c/w). note 3: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 4: delay times are measured using 50% levels with sw3 = v low = 6v, sw1 = 12v. note 5: the maximum output operating voltage for divider applications is 36v, the maximum input operating voltage for doubler applications is 36v. note 6: the maximum input operating voltage for divider applications is 72v, the maximum output operating voltage for doubler applications is 72v. note 7: when v cc > 15v, extv cc lower than v cc is recommended to improve efficiency and reduce ic temperature. note 8: all the voltage is referred to the gnd pin unless otherwise specified. note 9: extv cc is enabled only if v cc is higher than 7v. note 10: guaranteed by design. note 11: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum junction temperature may impair device reliability or permanently damage the device. electrical characteristics symbol parameter conditions min typ max units v low i sourcevlow source current to v low pin from i sense + i sense + = v high_sense = 24v, v low_sense = 11v, v low = 12v, timer = 1v 93 ma i sinkvlow sink current from v low pin to gnd i sense + = v high_sense = 24v, v low_sense = 13v, v low = 12v, timer = 1v 50 ma oscillator f s oscillator frequency range 100 1000 khz f nom nominal frequency v freq = 1.02v 500 khz i freq freq setting current v freq = 1.02v (note 3) C9.5 C10 C10.5 a faultb and hys_prgm r fault fault pull-down resistance v fault = 0.5v 200 400 i fault_leak fault leakage current v fault = 80v 2 a i hys_prgm hys_prgm setting current v hys_prgm = 1v (note 3) l C9.3 C10 C10.7 a v vlow_sense_fault v low_sense voltage trigger fault v vhigh_sense = 24v, v hys_prgm = 0v v vlow_sense ramp up v vlow_sense ramp down l l 12.2 11.6 12.3 11.7 12.4 11.8 v v v vhigh_sense = 24v, v hys_prgm = 5v v vlow_sense ramp up v vlow_sense ramp down l l 12.7 11.1 12.8 11.2 12.9 11.3 v v v vhigh_sense = 24v, v hys_prgm = 2.4v v vlow_sense ramp up v vlow_sense ramp down l l 14.15 9.5 14.3 9.65 14.45 9.8 v v uv comparator and pgood v uvth uv pin comparator threshold uv pin voltage rising 0.985 1.01 1.035 v v uvhys undervoltage hysteresis 120 mv r pgood pgood pull-down resistance v pgood = 0.5v 150 300 i pgood_leak pgood leakage current v pgood = 45v 1 a timer i timer timer pin current v timer < 0.5v or v timer > 1.2v (note 3) C3.5 a 0.5v < v timer < 1.2v (note 3) C7 a the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cc = 12v, v run = 5v, unless otherwise specified. lt c7820 7820fc
5 for more information www.linear.com/ltc7820 typical performance characteristics efficiency vs load current 48v to 24v voltage divider in figure 7 efficiency vs load current 24v to 12v voltage divider in figure 7 efficiency vs load current 24v to 48v voltage doubler in figure 8 efficiency vs load current 24v to C24v inverter in figure 9 steady state output ripple in figure 7 output voltage vs load current 24v to C24v inverter in figure 9 output voltage vs load current 48v to 24v voltage divider in figure 7 output voltage vs load current 24v to 48v voltage doubler in figure 8 load current (a) 1 efficiency (%) 100.0 95.5 99.5 98.5 97.5 96.5 99.0 98.0 97.0 96.0 95.0 11 7 7820 g01 15 9 5 13 3 f s = 150khz f s = 200khz f s = 250khz f s = 300khz load current (a) 0 efficiency (%) 98.0 93.5 97.5 96.5 95.5 94.5 97.0 96.0 95.0 94.0 93.0 6 7820 g04 10 8 42 f s = 150khz f s = 200khz f s = 250khz f s = 300khz load current (a) 0 output voltage (v) ?22.8 ?23.8 ?23.0 ?23.4 ?23.2 ?23.6 ?24.2 ?24.0 64 7820 g07 10 8 2 f s = 150khz f s = 200khz f s = 250khz f s = 300khz load current (a) 0 1 output voltage (v) 48.1 47.2 48.0 47.8 47.6 47.4 47.9 47.7 47.5 47.3 47.1 6 4 7820 g06 8 5 3 7 2 f s = 150khz f s = 200khz f s = 250khz f s = 300khz load current (a) ?1 1 output voltage (v) 24.05 23.60 24.00 23.90 23.80 23.70 23.95 23.85 23.75 23.65 23.55 11 7 7820 g05 15 9 5 13 3 f s = 150khz f s = 200khz f s = 250khz f s = 300khz load current (a) 1 efficiency (%) 100.0 95.5 99.5 98.5 97.5 96.5 99.0 98.0 97.0 96.0 95.0 11 7 7820 g02 15 9 5 13 3 f s = 150khz f s = 200khz f s = 250khz f s = 300khz load current (a) 0.5 efficiency (%) 100.0 95.5 99.5 98.5 97.5 96.5 99.0 98.0 97.0 96.0 95.0 5.5 3.5 7820 g03 7.5 4.5 2.5 6.5 1.5 f s = 150khz f s = 200khz f s = 250khz f s = 300khz t a = 25c, unless otherwise noted. load transient 0a-10a-0a 48v to 24v divider in figure 7 lt c7820 7820fc v out 200mv/div ac-coupled i load 5a/div 7820 g09 10s/div v in = 48v v out = 24v i load = 10a 150khz 200mv/div ac-coupled 200khz 200mv/div ac-coupled 250khz 200mv/div ac-coupled 7820 g08 50s/div f s = 250khz
6 for more information www.linear.com/ltc7820 typical performance characteristics driver voltage vs frequency, in figure 7 v cc shutdown current vs temperature short-circuit and retry 24v to 12v divider shutdown 48v to 24v voltage divider, run pin float intv cc line regulation v cc voltage (v) 0 10 intv cc voltage (v) 6 2 4 5 3 0 1 60 40 7820 g10 80 50 30 70 20 temperature (c) ?50 v cc current at shutdown (a) 85 60 80 70 75 65 40 50 45 55 100 50 7820 g11 150 0 v cc = 12v v cc = 48v v cc = 72v frequency (khz) 0 driver voltage (v) 5.8 4.8 5.6 5.2 5.4 5.0 4.0 4.4 4.2 4.6 1000800600400 7820 g12 1200 200 intv cc boost3-sw3 boost2-v low boost1-sw1 25c 125c ?45c 25c 125c ?45c 25c 125c ?45c 25c 125c ?45c t a = 25c, unless otherwise noted. start-up 48v to 24v voltage divider, run pin float input current during short circuit 48v to 24v divider divider efficiency vs c f ly in figure 11 voltage divider line transient t r = t r = 100s, f s = 500khz lt c7820 7820fc 20v/div 7820 g13 100ms/div v out 20v/div v in 20v/div run 5v/div sw3 200ms/div 20v/div 7820 g15 100ms/div v out 20v/div v in 20v/div run 5v/div sw3 v out 20v/div 7820 g14 5s/div v in 20v/div v out 20v/div sw3 50v/div i in 10v/div 20a/div 7820 g16 100s/div v in 5v/div v out 5v/div sw3 10v/div 7820 g17 fault 48v to 24v at 10a load 24v to 12v at 20a load quantity of 10f c f ly in parallel 8 10 12 14 16 96 97 10v/div 98 99 100 efficiency (%) 7820 g18 timer 5v/div sw3
7 for more information www.linear.com/ltc7820 pin functions uv (pin 8): undervoltage comparator input. if the uv pin voltage is lower than 0.9v, the pgood pin is pulled down while the controller keeps switching. if the uv pin voltage is higher than 1v and no faults exist, pgood pin is released. connect to intv cc if not used. i sense + (pin 27): current sense comparator positive input. kelvin connected to the positive node of the cur - rent sensing resistor. the current sensing resistor has to be connected to the drain of the very top mosfet. when the voltage between i sense + pin and i sense C pin is higher than 50mv , the controller indicates an overcurrent fault by pulling the fault pin down. the i sense + pin is also used to source 93ma current to the v low pin during the capacitor s pre-balancing time at power-up in voltage divider applications. connect directly to the drain of the very top mosfet if not used. i sense C (pin 28): current sense comparator negative input. kelvin connected to the negative node of the current sensing resistor. short to i sense + if not used. run (pin 6): run control input. forcing run below 1.14v shuts down the controller. when run is higher than 1.22v, internal circuitry starts up. there is a 1a pull-up current flowing out of run pin when the run pin voltage is below 1.14v and additional 5a current flowing out of run pin when the run pin voltage is above 1.22v. timer (pin 4): charge balance and fault timer control input. a capacitor between this pin and ground sets the amount of time to charge v low to v high_sense /2 voltage during power-up. it also sets the short-circuit retry time. see the application information section for details. fault (pin 9): open drain output pin. fault is pulled to ground when the v low_sense voltage is out of its window thresholds or the voltage between i sense + and i sense C is higher than 50mv. fault pin is also pulled to ground under intv cc uvlo. pgood (pin 7): open drain output pin. pgood is pulled to ground if there are any faults or if the uv pin indicates an undervoltage condition. hys_prgm (pin 3): a resistor connected between this pin and ground will program the two thresholds of the window comparator that monitors the voltage difference between v high_sense /2 and v low_sense . there is a 10a current flowing out of this pin. g4 (pin 15): high current gate drive for the bottom (synchronous) n-channel mosfet. voltage swing at this pin is from ground to intv cc . g3 (pin 17): high current gate drive for the third upper most n-channel mosfet. this is the output of the floating driver with a voltage swing from boost3 to sw3. g2 (pin 21): high current gate drive for the second upper most n-channel mosfet. this is the output of the floating driver with a voltage swing from boost2 to v low . g1 (pin 24): high current gate drive for the upper most n-channel mosfet. this is the output of the floating driver with a voltage swing from boost1 to sw1. sw1/sw3 (pin 25/pin 16): switch node connections. boost1, boost2, boost3 (pins 23, 22, 18): boot - strapped supplies to the floating drivers. capacitors are connected between these boost pins and their respective swn and v low pins. extv cc (pin 11): external power input to extv cc ldo. this ldo supplies intv cc power whenever extv cc is higher than 6.5v and v cc is higher than 7v . do not exceed 40v on this pin. intv cc (pin 12): output of the internal linear low dropout regulator. the driver and control circuits are powered from this voltage source. must be bypassed to power ground with a minimum of 4.7f ceramic or other low esr capacitor. v cc (pin 14) : power supply for internal circuitry and intv cc linear regulator. a bypass capacitor should be tied between this pin and the power ground. v high_sense (pin 1): kelvin sensing input. monitor the voltage of the drain of the top mosfet. lt c7820 7820fc
8 for more information www.linear.com/ltc7820 pin functions v low (pin 20): half supply from v high_sense . connect a bypass capacitor from this node to pgnd. v low_sense (pin 19): kelvin sensing input. monitors the voltage on v low . freq (pin 5): frequency set pin. there is a precision 10a current flowing out of this pin. a resistor to ground sets a voltage which in turn programs the frequency. see the applications information section for detailed information. nc (pins 2, 10, 13, 26): no connection. always keep these pins floating. these pins are intentionally skipped to isolate adjacent high voltage pins. gnd (exposed pad pin 29): signal and power ground. all small-signal components should connect to this ground, which in turn connects to system power ground at one point. the exposed pad must be soldered to the pcb, providing a local ground for the control components of the ic, which should be tied to system power ground under the ic. for inverter applications, gnd should connect to the negative output and all small signal components still referred to gnd pin. lt c7820 7820fc
9 for more information www.linear.com/ltc7820 block diagram + ? v high r f r sense m1 m2 m3 m4 g1 c b1 0.1f c f db1 control logic anti- shoot-through 24 boost1 23 i sense ? 28 i sense + 27 sw1 25 g2 c b2 1f c f ly db2 21 v low_sense 19 boost2 50ma 22 v low 20 g3 c b3 1f c vlow v low db3 17 boost3 18 sw3 16 fault 9 g4 c intvcc 4.7f 15 intv cc extv cc > 6.5v and v cc > 7v 12 gnd 7820 bd 29 v high_sense v low_sense vhys_prgm r2 500k 1 uvlo 120mv hysteresis overcurrent comparator 50mv threshold v cc ldo v cc 14 extv cc ldo extv cc intv cc 3.5a ~ 7a 11 pgood 1.01v 7 r3 500k 93ma + ? + ? uv 8 timer 4 v cc 1a ~ 6a run 6 intv cc 10a freq 5 intv cc 10a hys_prgm 3 osc lt c7820 7820fc
10 for more information www.linear.com/ltc7820 operation main control the ltc7820 is a constant frequency, open loop switched capacitor/charge pump controller for high power and high voltage applications. please refer to the block diagram for the following discussion on its operation. in steady state operation, the n-channel mosfets m1 and m3 are turned on and off in the same phase with around 50% duty cycle at a pre-programmed switching frequency. the n-channel mosfets m2 and m4 are turned on and off complementarily to mosfets m1 and m3. the gate drive waveforms are shown in figure 1. intv cc /extv cc power power for the quad n-channel mosfet drivers and most other internal circuitry is derived from the intv cc pin. normally an internal 5.5v linear regulator supplies intv cc power from v cc . if v cc is connected to a high input volt - age, an optional external voltage source on the extv cc pin enables a second 5.5v linear regulator and supplies intv cc power from the extv cc pin. to enable this more efficient second regulator, v cc needs to be higher than 7v and the extv cc pin voltage has to be higher than 6.5v. do not exceed 40v on the extv cc pin. each top mosfet driver is biased from the floating bootstrap capacitors c b , which are normally recharged during each off cycle through an external schottky diode when the respective top mosfet turns off. start-up and shutdown the ltc7820 is in shutdown mode when the run pin is lower than 1.14v . in this mode, most internal circuitry is turned off including the intv cc regulator and the ltc7820 consumes less than 100a current. all gates g1/g2/g3/ g4 are actively pulled low to turn off the external power mosfets in shutdown. releasing run allows an internal 1a current to pull up this pin and enable the controller. once the run pin rises above 1.22v, an additional 5a flows out of this pin. alternately, the run pin may be externally pulled up or driven directly by logic. do not exceed the absolute maximum rating of 6v on this pin. after the run pin is released and the intv cc voltage passes uvlo, the ltc7820 starts up and monitors the v high_sense and v low_sense voltages continuously. the ltc7820 starts switching only if v low_sense voltage is close to half of v high_sense voltage or both v low_sense and v high_sense voltages are close to gnd. in voltage divider applications, v low is pre-balanced to half the v high_sense voltage and the ltc7820 may start up with capacitors at different initial conditions. fault protection and thermal shutdown the ltc7820 monitors system voltage, current and temperature for faults. it stops switching and pulls down the fault pin when fault conditions occur. to clear voltage faults, the v low_sense pin voltage has to be within the figure 1. gate drive waveforms during phase 1, m1 and m3 are on and the flying capaci - tor c f ly is in series with c vlow . during phase 2, m2 and m4 are on and c f ly is in parallel with c vlow . the v low pin voltage is always close to half of the top voltage at the drain of mosfet m1 (refer to gnd pin) in steady state, and it is not sensitive to variable loads due to the very low impedance at its output. the ltc7820 does not regulate the output voltage with a closed-loop feedback system. however, it stops switching when fault conditions occur, such as v low pin voltage overvoltage or undervoltage, an overcurrent event or an overtemperature protection event. v gs m1 m2 m3 m4 ~ 50% du ty cycle ph ase 1 phase 2 phase 1 phase 2 7820 f01 t s lt c7820 7820fc
11 for more information www.linear.com/ltc7820 operationoperation programmed window around half of v high_sense voltage or the v high_sense and v low_sense voltages must be lower than 1v and 0.5v respectively. to clear the current fault, the voltage drop from i sense + pin to i sense C pin has to be lower than 50mv . to clear temperature faults, the ic temperature has to be lower than 165c. the fault pin may be pulled up by external resistors to voltages up to 80v. it can be used to control an external disconnect fet to isolate the input and output during fault conditions. high side current sensing for over current protection, the ltc7820 uses a sense resistor r sense to monitor the current. the sensing resistor has to be placed at the drain of the very top mosfet m1. for voltage divider and inverter applications, the current flows into the drain of the mosfet m1, so the i sense + pin should be connected to the sensing resistor then to the drain of the mosfet m1. for voltage doubler applications, the current flows out of the drain of the mosfet m1, so the i sense + pin should be connected directly to the drain of the mosfet m1 . see typical applications section for examples. in most applications, the current through the sense resistor is a pulse current and the peak value is much higher than the average load current. a rc filter on the i sense C pin, with a time constant lower than the switching frequency, may be used to set the precision average current protection. if overcurrent protection is not desired, short the i sense + and i sense C pins together and connect them to the drain of the top mosfet m1 directly. frequency selection the selection of switching frequency is a trade-off between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires larger capacitance to maintain low output ripple voltage and low output impedance. the freq pin can be used to program the controllers operating frequency from 100khz to 1mhz. there is a precision 10a current flowing out of the freq pin, so the user can program the controllers switching frequency with a single resistor to gnd. the voltage on the freq pin is equal to the resistance multiplied by 10a current (e.g. the voltage is 1v with a 100k resistor from the freq pin to gnd). in the linear region, the switching frequency, f s , can be estimated based on the equation: f s (khz) = r freq (k) ? 8 C 317khz figure 2 also shows the relationship between the voltage on the freq pin and switching frequency. power good and uv (pgood and uv pins) when the uv pin voltage is lower than 1v, the pgood pin is pulled low. the pgood pin is also pulled low when the run pin is low or when the ltc7820 is starting up. the pgood pin is released only when the ltc7820 is switching and uv pin is higher than 1v. the pgood pin will flag power bad immediately when the uv pin is low. however, there is an internal 20s power good mask and 120mv hysteresis when uv goes higher than 1v. the pgood pin may be pulled up by external resistors to sources up to 45v. pgood signal can be used to enable or disable the output loads. if the loads are switching mode converters or ldos with enable/run pins, this allows easy for interfacing. with proper setup on the uv pin, pgood can enable the loads at the output when the output voltage is above a certain value. pgood can also be used to control the run pin of another ltc7820 if two or more parts are cascaded to achieve higher step-down ratios. figure 2. relationship between switching frequency and voltage at the freq pin freq pin voltage (v) 0 switching frequency (khz) 1400 1200 800 400 1000 600 200 0 2 1 7820 f02 2.5 1.5 0.5 lt c7820 7820fc
12 for more information www.linear.com/ltc7820 the typical application on the first page of this data sheet is a ltc7820 voltage divider circuit. for voltage divider applications, the input voltage is at the drain of very top mosfet m1 and the output voltage is at the v low pin, which is connected to the source of mosfet m2 and the drain of mosfet m3. the output voltage is around half of the input voltage in steady state. alternately, by swap - ping the input and output voltages, the voltage divider cir cuit can be transformed into a voltage doubler cir cuit. for voltage doubler applications, the input voltage is at the v low pin while output voltage is available at the drain of the top mosfet m1 and equals two times the input voltage as shown in figure 8. similarly, for inverter ap - plications, the input voltage is applied between the drain of the top mosfet m1 and v low , and the output voltage equals the negative input voltage at the gnd pin with respect to the v low pin as shown in figure 9. for divider applications, if the load current is applied before startup or heavy resistive loads are connected to the vlow pin, the ltc7820 may not start up due to the limited drive ability of the pre-balance circuit. a disconnect fet may be used at the output for soft-start up. for doubler and inverter applications, a disconnect fet may also be required for soft start-up and shutdown. the disconnect fets in divider/ doubler/inverter applications may be also controlled by hot swap controllers to achieve more programmable slew rates and fault protections. voltage divider pre-balance before switching in voltage divider applications, the v low_sense voltage should be always close to v high_sense /2 in steady state. the voltages across the flying capacitors and v low ca- pacitors are close to each other and close to half of the input voltage. the charging inrush current is minimized during each switching cycle because the voltage difference between capacitors is small. however , without special methods such as the ltc7820 pre-charging circuitry, during start-up or fault conditions such as v low short to gnd, the difference between capacitors can be large and charging currents may be great enough to cause permanent mosfet damage. applications information when the power mosfets are on, ideally, the inrush charge current, i = v in C v cfly C v low r on _ m1 + r on _ m3 when switches m1 and m3 are on and: i = v cfly C v low r on _ m2 + r on _ m4 when switches m2 and m4 are on. both currents are lim - ited by the power mosfet saturation current. with very low r ds(on) of the external power mosfets, the inrush charge current could easily achieve several hundreds of amperes which can be higher than the mosfets safe operating area (soa). the ltc7820 provides a proprietary pre-balance method to minimize the inrush charging current in voltage divider applications. the ltc7820 controller detects the v low_sense pin voltage before switching and compares it with the v high_sense /2 internally. if the v low_sense pin voltage is much lower than the v high_sense /2, a current source will source 93ma current to the v low pin to pull the v low pin up. if the v low_sense pin voltage is much higher than the v high_sense /2, another current source will sink 50ma from v low pin to pull the v low pin down. if the v low_sense pin voltage is close to v high_sense /2 and within the pre-programmed window, both current sources are disabled and ltc7820 starts switching. if the v low_sense voltage is still within the window after 36 switching cycles, the fault pin is released. for voltage divider with pre-balance startup, the ltc7820 assumes no load current or a very small load current (less than 50ma ) at the v low (output) otherwise the v low volt- age cannot reach v high_sense /2 and the ltc7820 never starts up. this no load condition can be achieved by con - necting the fault pin to the enable pins of the following electrical loads such as switching regulators and ldos. if load current cannot be controlled off such as resistive loads, a disconnect fet is required to disconnect the load during startup as shown in the typical applications. lt c7820 7820fc
13 for more information www.linear.com/ltc7820 applications information if the ltc7820 divider input voltage is controlled by a front end supply or hot swap controller and ramps up slowly, the ltc7820 capacitor voltages are naturally bal - anced. in this case the pre-balance and no load start-up requirements are not necessary . voltage doubler and inverter startup and disconnect in voltage doubler and inverter applications, ltc7820 can startup without capacitor inrush charging current if the input voltage is ramping slowly up from zero. as long as the input voltage ramps up slow (in milliseconds), the output voltage can track the input voltage and the voltage difference between capacitors are always small resulting in no huge inrush currents. the slew rate control of the input voltage can be achieved by using a disconnect fet at input or using hot swap controllers as shown in the typical application section. different from voltage dividers, the voltage doubler and inverter applications have to start up from zero input voltage every time, but they can start up with heavy load currents directly. note that voltage divider applications can also startup with a slow ramping input voltage from zero to the steady state operation if there is a hot swap in front of the ltc7820, (pre-balance is not required). overcurrent protection the ltc7820 provides overcurrent protection through a sensing resistor placed on the high voltage side. a precision rail to rail comparator monitors the differential voltage between the i sense + pin and the i sense C pin which are kelvin connected to a sensing resistor. whenever the i sense + pin voltage is 50mv higher than the i sense C pin voltage, an over current fault is triggered and the fault pin is pulled down to ground. at the same time the ltc7820 stops switching and starts retry mode based on the timer pin setup. the overcurrent fault will be cleared when the timer pin voltage reaches 4v and the voltage across the sensing resistor is less than 50mv. the current through the sensing resistor is a pulse current during charging/ discharging of the flying capacitors, which may result a voltage higher than the 50mv threshold at heavy loads. to prevent the inrush current from falsely triggering the overcurrent protection, an rc filter is required at the i sense + pin and i sense C . the rc filter timer constant has to be larger than a switching period. typically a 100 and 0.1f filter is good for most of applications. due to the current flowing into the i sense + pin, the resistor of the rc filter has to be placed at the i sense C pin. i sense + pin needs to be connected to the sensing resistor directly. the current limit can be selected by choosing different sense resistor values. for example, the 10m sense resistor sets current limit at 50mv/10m = 5a ideally. due to the switching ripple, the actual current limit is always lower than the ideal case. in real circuits, the current limit is around 4.2a with 0.1f/100 filter and 200khz switch - ing frequency. the ltspice ? simulation tool can be used to quantify the switching ripple. the overcurrent protection can also be used in doubler and inverter applications for overcurrent and short-circuit conditions at both startup and steady state operation. if over current protection is not used, short the i sense + pin and the i sense C pin together and connect them to the drain of the top mosfet m1. window comparator programming in normal operation, v low_sense voltage should be always close to half of the v high_sense voltage. a floating win - dow comparator monitors the voltage on the v low_sense pin and compares it with v high_sense /2. the hysteresis window voltage can be programmed and is equal to the voltage at the hys_prgm pin. there is a precision 10a current flowing out of hys_prgm pin. a single resistor from hys_prgm pin to gnd sets the hys_prgm pin voltage, which equals the resistor value multiplied by 10a current (e.g. the voltage is 1v with a 100k resistor from the hys_prgm pin to gnd). with a 100k resistor on the hys_prgm pin, the v high_sense /2 voltage has to be within a (v low_sense 1v ) window during startup and normal operation, otherwise a fault is triggered and the ltc7820 stops switching. lt c7820 7820fc
14 for more information www.linear.com/ltc7820 v hys_prgm (v) 0 v low_sense window voltage (v) 2.5 2 1 1.5 0.5 0 4 2 7820 f03 5 3 1 applications information the hysteresis window voltage can be linearly programmed from 0.3v to 2.4v as shown in figure 3 with different resistor values on the hys_prgm pin. if the hys_prgm pin is tied to intv cc , a default 0.8v hysteresis window is applied internally. the hysteresis window voltage has to be programmed large enough to tolerate the v low pin volt- age ripple and voltage drop at maximum load conditions. effective open loop output resistance and load regulation the lt c7820 does not regulate the output voltage through a closed loop feedback system. however, the output voltage is not sensitive to load conditions due to the low output resistance when it is operating with large flying capacitors and high switching frequency. the thevenin equivalent circuit of voltage divider circuit is shown in the figure 4. when duty cycle is around 50%, r out = 1 + e C 1 4f s r ds(on) c fly 4f s c fly 1C e C 1 4f s r ds(on) c fly ? ? ? ? ? ? ? ? ? ? where: f s is the switching frequency c f ly is the flying capacitor r ds(on) is the on resistance of one mosfet ( g1 to g4) v in v in /2 r out c f ly c vlow g1 g2 g3 g4 sw1 sw3 v low v low c vlow 7820 f04 during an input line transient, as long as the change of the input voltage in each switching cycle is less than the window hysteresis voltage, ltc7820 keeps switching and the output voltage tracks the input voltage cycle by cycle. if the input voltage step is large enough to force v low_sense out of the window within one switching period, a fault is triggered. the ltc7820 stops switching and starts its retry sequence based on the timer pin setup. to make the window comparator work precisely, v high_sense and v low_sense pins are provided for kelvin connection to the capacitor at the drain of the top mosfet m1 and the capacitors from v low to gnd respectively. small rc filters may be used on these two pins to reject noise higher than the switching frequency. figure 3. relationship between hys_prgm pin voltage and v low_sense window comparator voltage figure 4. thevenin equivalent circuit of voltage divider lt c7820 7820fc
15 for more information www.linear.com/ltc7820 at low switching frequencies, r out = 1/(4f s c f ly ). as frequency increases, r out finally approaches 2r ds(on) . in high power applications, it is suggested to select the switching frequency around 1/(16c f ly r ds(on) ) or higher for decent load regulation and efficiency. at heavy load conditions, the output voltage will drop from v in /2 by r out ? i load . in many applications, multi-layer ceramic capacitors (mlcc) are selected as flying capacitors. the voltage coefficients of mlcc capacitors strongly depend on the type and size of capacitors. normally larger size x7r mlcc capacitors are better than x5r in terms of voltage coefficient. the capacitance still drops 20% to 30% with high dc bias voltage. capacitance derating needs to be considered when estimating the output resistance of these switched capacitor circuits. intv cc regulators and extv cc the ltc7820 features an internal pmos ldo that supplies power to intv cc from the v cc supply. intv cc powers the gate drivers and most of the ltc7820 s internal circuitry. the linear regulator regulates the voltage at the intv cc pin to 5.5v when v cc is greater than 6v . extv cc connects to intv cc through another pmos ldo and can supply the needed power when its voltage is higher than 6.5v and v cc is higher than 7v. each of these can supply a peak current of 150ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the intv cc and gnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the ltc7820 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5.5v linear regula - tor from v cc or the linear regulator from extv cc . when the voltage on the extv cc pin is less than 6.5v, the linear regulator from v cc is enabled. power dissipation for the ic in this case is highest and is equal to v cc ? i intvcc . the gate charge current is dependent on operating frequency. the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, the ltc7820 intv cc current is limited to less than 27ma from a 48v supply in the ufd package and not using the extv cc supply: t j = 70c + (27ma)(48v)(43c/w) = 125c where ambient temperature is 70 c and thermal resistance from junction to ambient is 43c/w to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating at maximum v in . when the voltage applied to extv cc rises above 6.5v and v cc above 7v , the intv cc linear regulator is turned off and the extv cc linear regu- lator is turned on. using the extv cc allows the mosfet driver and control power to be derived from other high efficiency sources such as the v low pin of a 48v to 24v voltage divider or other voltage rails in the system. using extv cc can significantly reduce the ic temperature in high v in applications. tying extv cc to the output (24v ) reduces the junction temperature in the previous example to: t j = 70c + (27ma) (24v) (43c/w) = 98c do not apply more than 40v to the ext v cc pin. topside mosfet driver supply (c b , d b ) external bootstrap capacitors c b1 /c b2 /c b3 in the block diagram, connected to the boost pins, supply the gate drive voltages for the top side mosfets m1/m2/m3. capacitor c b3 in the block diagram is charged though external schottky diode d b3 from intv cc when the sw3 pin is low. capacitor c b2 is charged through d b2 from boost3 when the sw3 pin is high. capacitor c b1 is charged through d b1 from boost2 when the sw1 pin is low. when the mosfets m1/m2/m3 are to be turned on, the driver places the c b1 /c b2 /c b3 voltage across the gate source of the mosfets m1/ m2/ m3 . this enhances the mosfets and turns them on. the switch node voltage, sw1/sw3, rises to i sense + /v low and the boost pin follows. with continuous switching, the gate driver voltages on c b1 /c b2 /c b3 are: v cb3 = v intvcc C v db3 v cb2 = v intvcc C v db3 C v db2 v cb1 = v intvcc C v db3 C v db2 C v db1 applications information lt c7820 7820fc
16 for more information www.linear.com/ltc7820 applications information the value of the boost capacitors, c b1 /c b2 /c b3 , needs to be 100 times that of the total input capacitance of the topside mosfet(s). the standard 6.3v mlcc ceramic ca - pacitors are good for c b1 /c b2 /c b3 . the reverse breakdown of the external schottky diodes must be greater than the maximum operation voltage between the v low and gnd pins. when adjusting the gate drive level, the final arbiter is the threshold voltage of the top mosfet m1 . the top driver voltage v cb1 has to be higher than the top fet m1 threshold voltage in all conditions. logic level mosfet should be used, otherwise lower operating switching frequency and lower forward voltage drop diodes are necessary to raise the gate driver voltages. undervoltage lockout the ltc7820 has a precision uvlo comparator constantly monitoring the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 4.9v . to prevent oscillation when there is a disturbance on intv cc , the uvlo com- parator has 200mv of precision hysteresis. another way to detect an under voltage condition is to monitor the input supply . because the run pin has a pre - cision turn-on reference of 1.22v, one can use a resistor divider to the input to turn on the ic when the input volt - age is high enough. an extra 5a of current flows out of the run pin once the run pin voltage passes 1.22v . one can program the hysteresis of the run comparator by adjusting the values of the resistive divider. fault response and timer programming the ltc7820 stops switching and pulls the fault pin low during fault conditions. a capacitor connected from the timer pin to gnd sets the retry time to start-up if fault conditions are removed. a typical waveform on the timer pin during a fault condition is shown in figure 5. after the fault pin is pulled low, a 3.5a pull-up current flows out of timer pin and starts to charge the timer capacitor. the pull-up current increases to 7a when the timer pin voltage is higher than 0.5v and back to 3.5a when the timer pin voltage is higher than 1.2v. the timer pin will be strongly pulled down whenever the fault conditions are removed or the timer pin voltage is higher than 4v. when the timer pin voltage is between 0.5v and 1.2v , the internal pre-balance circuit will source or sink current to the v low pin and regulate the v low pin to v high_sense /2 with around 93ma/50ma capability. the pre-balance time can be calculated based on the capacitor c timer on the timer pin: t pre-balance = c timer ? 0.7v/7a so the pre-balance time is 100ms/f (e.g. the pre-balance time is 10ms with 0.1f c timer ). for voltage divider applications, the output capacitors and the flying capacitors are pre-balanced to half of the input voltage during the startup. assuming zero initial condi - tions, the time to charge the capacitors, t charge , can be estimated from the equation: t charge = (c out + c f ly ) ? v in /2/ 93ma 7820 f05 fault low 3.5a charge timer pin 3.5a charge timer pin 7a charge timer pin 0.5v 1.2v 4v pre-balance time fault release figure 5. timer behavior during fault or startup lt c7820 7820fc
17 for more information www.linear.com/ltc7820 select the c timer such that the t charge < t pre-balance . if the flying capacitor c f ly and the output capacitor are very large and input voltage is high, it may take several pre-balance time periods to pre-balance the v low pin to v high_sense /2 with a fixed c timer . a longer start-up time is expected. if there is a resistive load on the output, the load current needs to be smaller than 93ma and still meet t charge = (c out + c f ly ) ? v in /2/(93ma C i load ) < t pre- balance . otherwise a disconnect fet may be required to disconnect the load during startup. input/output capacitor and flying capacitor selection in high power switched capacitor applications, large ac currents flow through the flying capacitors and input/ output capacitors. low esr ceramic capacitors are highly recommended for high power switch capacitor applica - tions. make sure the maximum rms capacitor current is within the spec; or higher rms current rated capacitors are preferred. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose capacitors rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. the rms current on the flying capacitors depends on their capacitance and the switching frequency. higher capaci - tance and higher switching frequency results in lower rms current. for a good trade-off between efficiency and power density , the rms current on the flying capacitors should be lower than 140% of the maximum load current. if there are n identical flying capacitors in parallel, the maximum rms current through each capacitor is: i rms_cfly = i out(max) ? 140%/ n the input capacitor rms current is approximately half of the load current. the input capacitor has to be selected to accommodate the maximum load conditions. ltspice simulation tool can be used to quantify the rms current. applications information power mosfets and schottky diodes selection four external n-channel mosfets must be selected for each ltc7820 controller. four internal gate drivers are designed to drive the mosfets. the driver voltages are decided by the intv cc voltage, schottky diodes forward voltage drop and switching frequency. the lowest driver voltage is the top mosfet m1 drive voltage running at high switching frequency and cold temperature. it is normally around 4.2v . consequently, logic-level threshold mosfets must be used in most applications. be aware that the threshold voltage of some logic-level mosfet varies with temperature. if switching frequency is high and temperature range is wide for specific applications, the top driver voltage of mosfet m1 may be as low as 4v , and sub-logic level threshold mosfets (v gs(th) < 3v) should be used. selection criteria for the power mosfets also include the on-resistance r ds(on) , output capacitance c oss , input voltage, and maximum output current. gener - ally, low r ds(on) and low c oss mosfets are preferred in switched capacitor applications since they will minimize both conduction loss and switching loss. for a given input and output voltage, the uppermost mosfet m1 always sees high voltage during start-up and shutdown. the drain to source voltage of m1 has to be high enough to survive at full input voltage range. other mosfets normally only see half of the input voltage, so the breakdown voltage of m2/m3/m4 can be lower than m1 to optimize r ds(on) and c oss . if the reliability of m1 is a major concern, the same high voltage mosfets could also be used as m2/ m3/m4 to protect against m1 short conditions. external schottky diodes are needed for the bootstrap circuits, and provide voltage for the floating drivers. to minimize the voltage drop on the top gate driver, low forward voltage drop schottky diodes are preferred with load current in the range of 10ma to 50ma. the reverse breakdown voltage of the diodes should be high enough to survive at the maximum operation voltage between the v low and gnd pins. lt c7820 7820fc
18 for more information www.linear.com/ltc7820 applications information pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. 1. are the top 2 n-channel mosfets m1 and m2 located within 1cm of each other? are the bottom 2 n-channel mosfets m3 and m4 located within 1cm of each other? 2. is the exposed gnd pad solid connected to the source of bottom mosfet m4 and the negative terminal of c vlow capacitors? in divider and doubler applications, a solid ground plane is preferred for noise and thermal improvement. 3. are the i sense + and i sense C leads routed together with minimum pc trace spacing? the filter capacitor between i sense + and i sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 4. is the intv cc bypassing capacitor connected close to the ic, between the intv cc and the ground plane? this capacitor carries the mosfet drivers current peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and gnd can substantially improve noise performance. 5. keep the switching nodes (sw1, sw3), top gate nodes (g1, g2, g3 ), and boost nodes (boost1, boost3) away from sensitive small-signal nodes. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc7820 and occupy minimum pc trace area. 6. use a modified star ground technique: a low impedance, large copper area central grounding point on the same side of the pc board as the input and output capaci - tors with tie-ins for the bottom of the intv cc bypass capacitor. figure 6 illustrates the high current paths requiring thick and wide copper trace connection. refer to demo boards on www .linear.com/demo for pcb layout examples. pc board layout debugging start with one controller at a time. monitor the switching nodes (sw1/sw3 pin) and probe the v low voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the full input voltage range down to dropout. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementation. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output cur - rents, look for capacitive coupling between the boost, sw, g1/2/3/4 connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the gnd pin of the ic. lt c7820 7820fc
19 for more information www.linear.com/ltc7820 applications information figure 6. high current path in printed circuit board layout diagram 7820 f06 lt c7820 7820fc db1 c f ly c opt c fly1 c fly2 c opt1 c opt2 c vlow1 c vlow2 c in m4 v cc v high_sense uv hys_prgm pgood freq fault fault gnd intv cc r sense g3 g4 intv cc timer g2 ltc7820 boost3 sw3 v low_sense v low c vlow boost2 boost1 sw1 g1 intv cc extv cc run i sense + i sense ? v in m3 pgood v out m2 m1 db3 db2
20 for more information www.linear.com/ltc7820 applications information design example as a design example using ltc7820 for a high voltage high power voltage divider, assume v in = 48v (nominal), v in = 55v (maximum), v out = 24v (nominal), i out = 15a (maximum). for high power and high voltage applications, always start with a low switching frequency e.g. 200khz to minimize the switching losses. to set the 200khz switching frequency, a 60.4k /1% resistor is connected from freq pin to ground. setting the c f ly voltage ripple to be 2% of the output voltage is a good starting point with trade-off between efficiency and power density. the c f ly can be calculated based on the equation below: c fly = i out(max) 2f s v cfly(ripple) = 15a 2 ? 200khz ? 0.48v = 78.125f considering the ceramic capacitance derating at 24v dc bias voltage, 16 of 10f/x7r/50v ceramic capacitors are paralleled as flying capacitors. the worst case rms current may be 40% higher than the maximum output current. so the worst case rms on each capacitor can be estimated by this equation: i rms(max) = i out(max) ? 140% n = 15a ? 140% 16 = 1.3125a where n is the number of flying capacitors. double check and make sure the rms current on each capacitor is below the ripple current ratings and temperature rise is below the limits. the output capacitor selection is similar to the flying capacitor selection. more output capacitors resulting smaller output voltage ripple. because of the lower rms current, the output capacitor value can be much less than the flying capacitor. some of the capacitors may be con - nected between input and output to serve as input/output capacitors at th e same time, as shown in figure 6. however the voltage rating of those capacitors has to be selected based on the input voltage instead of the output voltage. for mosfet selection, the top mosfet m1 drain to source voltage has to be higher than the maximum input voltage, while the other three mosfets drain to source voltage only needs to be higher than half of the maximum input voltage. since logic level fets are preferred, an infineon bsc100n06ls is chosen as the top mosfet m1 and bsc032n04ls are used as m2/3/4. based on the output resistance equation in the application section, the output resistance is around 20m , which will result 300mv drop at the 24v output at 15a load current. in reality, due to the finite dead time and parasitic resistance on the pcb, the voltage drop may be higher than the calculated value. taking into account the output voltage ripple, a window comparator with 1v programmed hysteresis is used to monitor the output voltage and compares it with the half of the input voltage during operation. to set the 1v hys - teresis, a 100k/1% resistor is connected from hys_prgm pin to ground. lt c7820 7820fc
21 for more information www.linear.com/ltc7820 typical applications figure 7. high efficiency 48v/24v to 24v/12v, 15a voltage divider lt c7820 7820fc m4 c vlow 10f 6 c f ly 10f 16 c top 10f 4 bsc032n04ls m3 bsc032n04ls m2 bsc100n06ls m1 0.1f db3 cmdsh-4 db2 cmdsh-4 c b1 0.1f c b2 1f c b3 1f db1 cmdsh-4 0.1f 0.1f 10 10k 10k 2.2f 0.1f v cc v high_sense uv hys_prgm pgood freq fault fault 10k gnd intv cc g3 g4 intv cc timer g2 ltc7820 boost3 sw3 100k v low_sense v low boost2 boost1 sw1 g1 intv cc extv cc run i sense + 60.4k i sense ? 48v/24v 24v/12v 15a* pgood *load current applied after start-up 12v v in v out 7820 f07 4.7f 10 bsc032n04ls
22 for more information www.linear.com/ltc7820 typical applications figure 8. high efficiency 24v to 48v, 7.5a voltage doubler with disconnect fet at input + + lt c7820 7820fc m4 bsc032n04ls r sense 0.005 d3 cmhz5236b m disconnect sud50n04-8m8p 10f 50v 6 1f m3 bsc032n04ls m2 bsc032n04ls m1 bsc100n06ls db3 cmdsh-4 0.47f 1f db2 cmdsh-4 0.1f db1 cmdsh-4 0.1f 0.1f 10 100 0.1f c f ly 10f 50v 16 12v 10f 6 0.22f r19 10k r20 10k v cc v high_sense uv hys_prgm pgood freq 10k fault fault gnd intv cc g3 g4 intv cc timer g2 ltc7820 100k boost3 sw3 v low_sense v low boost2 boost2 boost1 sw1 g1 intv cc 10k extv cc run i sense + i sense ? boost2 24v v out 48v 7.5a v in 0.1f 7820 f08 68k 10f 4 33f 80v 36m 100f 35v 28m 4.7f 10
23 for more information www.linear.com/ltc7820 figure 9. high efficiency 24v to C24v, 10a voltage inverter with hot swap at input + typical applications lt c7820 7820fc m4 bsc032n04ls *optional discharging components for fast startup. 10f 8 1f m3 bsc032n04ls m2 bsc032n04ls m1 bsc032n04ls v out db3 cmdsh-4 1f 0.1f db2 cmdsh-4 0.1f db1 cmdsh-4 0.1f v out 0.1f 10 c f ly 10f 16 10f 8 10k 4.7f bat54ws 0.01f v cc v high_sense uv hys_prgm pgood freq fault fault 10k gnd intv cc g3 g4 intv cc timer g2 ltc7820 boost3 sw3 v out sw3 v low_sense v low boost2 boost1 sw1 g1 intv cc extv sw3 cc run 10k i sense + i sense ? 24v v in hot swap circuitry (e.g. lt4256) v out v out v out v out 100 75k v out 0.1f v out v out ?24v 10a uv out gnd in 2.2f 100v 8 100k 4.7f 7820 f09 100k r opt * 10 m opt * bss123l 68f 50v 30m 2 10
24 for more information www.linear.com/ltc7820 figure 10. high efficiency 24v to 12v, 10a voltage divider with hot swap at input + typical applications lt c7820 7820fc *optional discharging components for fast startup. 10f 8 1f m3 bsc032n04ls m2 bsc032n04ls m1 bsc032n04ls db3 cmdsh-4 1f db2 cmdsh-4 0.1f 0.1f db1 cmdsh-4 0.1f 0.1f 10 c f ly 10f 16 10f 8 68f 35v 10k 0.01f v cc 4.7f v high_sense uv hys_prgm pgood freq fault fault gnd intv cc g3 10k g4 intv cc timer g2 ltc7820 boost3 sw3 sw3 v low_sense v low 10k boost2 boost1 sw1 g1 intv cc extv cc run i sense + i sense ? 24v 75k v in hot swap circuitry (e.g. lt4256) v out 0.1f v out 12v 10a uv out gnd in 100k 4.7f 7820 f10 10k r opt * 10 m opt * bss123l 10 m4 bsc032n04ls
25 for more information www.linear.com/ltc7820 typical applications figure 11. high efficiency 48v to 12v, 20a voltage divider lt c7820 7820fc 1f timer g2 ltc7820 boost3 sw3 boost2 boost1 sw1 g1 run bsc032n04ls v out vmid *pgood2 * load current applied after start-up pgood2 may be used to enable the load current intv cc1 0.1f intv cc2 v low_sense v low intv cc m3 extv cc i sense + i sense ? extv cc intv cc2 c fly2 10f 16 v out 12v 20a* v low_sense v low intv cc bsc032n04ls m2 bsc100n06ls m1 db3 cmdsh-4 1f 100k db2 cmdsh-4 0.1f db1 cmdsh-4 0.1f 0.1f 10 c fly1 10f 8 c top1 10f 2 100k c top2 10f 4 c out 10f 6 c mid 10f 2 2.2f 0.1f 100k 100k 10k 100k 4.7f 10k 10 bsc011n03ls m8 1f bsc011n03ls m7 bsc011n03ls m6 bsc011n03ls m5 60.4k db6 cmdsh-4 1f db5 cmdsh-4 0.1f db4 cmdsh-4 0.1f 0.1f 4.7f 10 2.2f 10k 10k v high_sense v cc v high_sense v cc uv hys_prgm 10 pgood freq fault gnd g3 g4 timer g2 ltc7820 boost3 bsc032n04ls sw3 boost2 boost1 sw1 g1 run i sense + i sense ? v in 48v v mid m4 v out uv hys_prgm pgood freq fault gnd 7820 f11 g3 g4
26 for more information www.linear.com/ltc7820 package description please refer to http://www.linear.com/product/ltc7820#packaging for the most recent package drawings. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wghd-3). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0816 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev c) lt c7820 7820fc
27 for more information www.linear.com/ltc7820 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. revision history rev date description page number a 06/17 removed tg/bg from ec tables 3s b 07/17 changed the # of switching cycles in voltage divider section modified intv cc pin description changed hysteresis voltage in power good section 12 7 11 c 10/17 corrected hot swap part number call-out. 23, 24 lt c7820 7820fc
28 for more information www.linear.com/ltc7820 ? analog devices, inc. 2017 lt 1017 rev c ? printed in usa www.linear.com/ltc7820 related parts typical application figure 12. high efficiency 24v to 12v, 15a voltage divider with disconnect fet at output part number description comments LTC3255 48v fault protected 50ma step-down charge pump 4v v in 48v, 2.4v v out 12.5v, i q = 20a, 3mm 3mm dfn-10, msop-10 ltc3895 150v low i q , synchronous step-down dc/dc controller 4v v in 140v, 150v p-p , 0.8v v out 24v, i q = 50a pll fixed frequency 50khz to 900khz lt c3891 60v, low i q , synchronous step-down dc/dc controller with 99% duty cycle 4v v in 60v, 0.8v v out 24v, i q = 50a pll fixed frequency 50khz to 900khz lt c3897 60v multiphase synchronous boost controller with input/ output protection 4v v in 60v, v out up to 60v, in-rush current control, overcurrent protection and output disconnect ltc3784 60v single output, low i q multiphase synchronous boost controller 4.5v (down to 2.3v after start-up) v in 60v, v out up to 60v, pll fixed frequency 50khz to 900khz, 4mm 5mm qfn-28, ssop-28 lt c3769 60v low i q synchronous boost controller 4.5v (down to 2.3v after start-up) v in 60v, v out up to 60v, pll fixed frequency 50khz to 900khz, 4mm 4mm qfn-20, tssop-20 lt c4442 high speed synchronous n-channel mosfet drivers up to 38v supply v oltage, 6v v cc 9.5v, 2.4a peak pull-up/5a peak pull-down, msop-8 lt ? 4256-1/ lt4256-2 positive high v oltage hot swap controllers 10.8v v in 80v, active current limit, auto-retry or latchoff ltm4636/ ltm4636-1 40a , dc/dc module regulator 4.7v v in 15v. 0.6v v out 3.3v, 16mm 16mm 7.07mm (bga) lt m ? 4650/ ltm4650a dual 25a or single 50a dc/dc module regulator 4.5v v in 15v, 0.6v v out 1.8v, 16mm 16mm 5.01mm (bga) 4.5v v in 16v, 0.6v v out 5.5v, 16mm 16mm 5.01mm (bga) lt c7820 7820fc r sense 0.005 d3 cmhz5236b c vlow 10f 6 1f m3 bsc032n04ls m2 bsc032n04ls m1 bsc032n04ls db3 cmdsh-4 1f db2 cmdsh-4 0.1f 0.1f db1 cmdsh-4 0.1f 0.1f 10 100 0.1f c f ly 10f 16 220f 1f 10k r19 10k r20 10k 4.7f c top 10f 4 v cc v high_sense uv hys_prgm pgood 10k freq fault fault gnd intv cc g3 g4 intv cc timer g2 10k ltc7820 boost3 sw3 v low_sense v low boost2 boost2 boost1 sw1 g1 80k intv cc extv cc run i sense + i sense ? v in 24v boost2 v out 12v 15a v out 7820 f12 4.7f m disconnect sud50n04-8m8p 10 m4 bsc032n04ls

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